🚌 CAN Physical Layer & Termination

CAN is a differential bus, which means the message does not live at a node, it lives in the gap between two wires. To read it, drive it, and trust it, you have to think in the same order the bus itself does: the differential voltage decides the bit, and the termination decides whether that voltage is even readable. Get the levels right and the termination wrong and you have a beautiful signal that arrives as mush. This lesson walks that order, from the two voltage states up through the resistors that make them legible.

By the end, you can

1. Explain the recessive and dominant CAN states in terms of CANH, CANL, and their differential voltage
2. Calculate the differential voltage from a pair of CANH/CANL readings and decide which bit a receiver sees
3. Justify why a CAN bus needs 120 Ω at each physical end, and predict the unpowered CANH-CANL resistance for 0, 1, or 2 terminators
4. Run the 60-ohm health check on an unpowered bus and diagnose a missing or doubled terminator from the reading
5. Explain why every node must share one bit rate and sample near the same point in the bit

Intuition first

Picture two swimmers floating side by side in a pool, holding hands. When the bus is idle, both of them just float at the same level, say chest-deep, doing nothing. That shared floating level is the recessive state: nobody is pushing, weak springs hold both wires at the same middle voltage, and the difference between them is essentially zero. Recessive is a logical 1, and it is also what the bus looks like when no one is talking.

Now one swimmer decides to send a bit. They do not drift. They actively shove: one swimmer pushes up out of the water while the other ducks down, and they spread apart by a fixed, deliberate amount. That forced spread is the dominant state, a logical 0. The receiver does not care how deep the pool is or whether the whole pool is sloshing (that is common-mode noise, and you met it in lesson 26). It only watches the gap between the two swimmers. A wide gap means dominant; no gap means recessive.

Two properties fall out of this picture and run the rest of the lesson. First, dominant wins: if one swimmer shoves while another tries to drift, the shove dominates, because an active push always overrides a passive float. That is the whole basis of CAN arbitration. Second, the pushing only produces a clean, readable gap if the water does not slosh back and forth after each shove. The resistors that stop that slosh are the termination, and they are the second half of this lesson.

The two states, in volts

A high-speed CAN bus carries two wires, CANH and CANL, and a receiver decides the bit purely from the difference $V_\text{diff} = V_\text{CANH} - V_\text{CANL}$. There are exactly two states it cares about.

Recessive (logical 1). No transmitter is driving. Weak internal biasing pulls both wires toward a common middle level of about $2.5\ \text{V}$, so

$$V_\text{CANH} \approx 2.5\ \text{V}, \quad V_\text{CANL} \approx 2.5\ \text{V}, \quad V_\text{diff} \approx 0\ \text{V}.$$

The receiver treats any difference below roughly half a volt as recessive. This is the idle state and the logical 1.

Dominant (logical 0). A transmitter actively drives the pair apart. CANH rises and CANL falls, symmetrically around that same $2.5\ \text{V}$ center:

$$V_\text{CANH} \approx 3.5\ \text{V}, \quad V_\text{CANL} \approx 1.5\ \text{V}, \quad V_\text{diff} \approx 2\ \text{V}.$$

Notice the average $(V_\text{CANH} + V_\text{CANL})/2$ stays near $2.5\ \text{V}$ in both states. That is deliberate: the common-mode level barely moves, so noise that lands on both wires together rides out at the receiver and only the $2\ \text{V}$ dominant difference (or the near-zero recessive difference) carries information. CAN is your lesson-26 differential idea built into a wire protocol.

Why the bus needs termination

Drive a fast edge into a long pair of wires and the edge does not just arrive at the far end. It travels down the line like a wave, hits the far end, and if the far end does not absorb it, the wave bounces back. That reflected wave races back toward the transmitter, bounces again, and the result is ringing: the voltage overshoots, undershoots, and wobbles around the value you wanted for several round trips. On a bus trying to clock bits at hundreds of kilohertz or a megahertz, that ringing can still be sloshing when the receiver samples, and a sample taken mid-wobble reads the wrong bit.

The cure is to make the far end look, electrically, like more cable. A wire pair has a characteristic impedance set by its geometry, about $120\ \Omega$ for the twisted pair CAN uses. If you bridge the two wires with a resistor equal to that impedance, an arriving wave sees no discontinuity, dumps its energy into the resistor as heat, and nothing reflects. That is why a CAN bus puts a 120 Ω resistor across CANH-CANL at each physical end of the trunk, never in the middle and never just at one end. Two ends, two resistors. The termination is not an optional nicety bolted on to clean up the signal. It is part of the signaling system: without it the dominant pulse rings, and with a single terminator half the energy still reflects off the open end.

Read the diagram as one straight trunk with the nodes tapping on with short stubs. The two $120\ \Omega$ resistors live only at the two physical ends. Keep the stubs short, so any small reflections off a node settle long before the bit is sampled, and never bury a terminator in the middle of the run, where it would absorb energy that still has bus left to travel.

The 60-ohm health check

Here is the payoff, and it is the single most useful CAN measurement on a bench. Power the bus completely off. Put a multimeter on ohms across CANH and CANL. The two end terminators are now just two resistors wired in parallel across the same two wires, so the meter reads them in parallel:

$$R_\text{bus} = \frac{120\ \Omega \times 120\ \Omega}{120\ \Omega + 120\ \Omega} = \frac{120\ \Omega}{2} = 60\ \Omega.$$

So a correctly terminated, unpowered CAN bus reads about 60 Ω across CANH-CANL. That one number is a complete go/no-go test, because the failure modes each move it in a recognizable direction:

• ≈ 60 Ω: two terminators present. Healthy.
• ≈ 120 Ω: only one terminator. The other end is open, the bus rings, and frames corrupt under load. This is the classic “I added a node and forgot the terminator” fault.
• ≈ 40 Ω: three terminators (someone added a node with termination built in to a bus that was already terminated). $120 / 3 = 40\ \Omega$. Over-terminated, the drivers strain, levels sag.
• Open / very high: no termination at all. The bus is effectively unterminated and edges ring badly.

You measure it cold because, powered, the transceivers and biasing networks are in parallel with those resistors and the reading no longer means “how many terminators do I have.” Off, the resistors stand alone, and $60\ \Omega$ is the truth. Two probes, three seconds, and you have ruled in or ruled out the most common physical-layer fault on the bus before you ever touch the firmware.

Everyone agrees on the clock that isn’t there

CAN sends no separate clock wire. The bits are self-clocked: receivers resynchronize on the edges in the data itself. For that to work, every node has to be set to the same bit rate (250 kbit/s, 500 kbit/s, 1 Mbit/s, whatever the bus runs), and every node has to look at each bit at roughly the same instant.

That instant is the sample point, and on CAN it sits late in the bit, around $75\%$ to $87.5\%$ of the bit time. A bit is divided into small slices called time quanta, grouped into segments, and the sample point is placed after the propagation and the first phase segment so the signal has had time to travel the whole bus and settle. Put the sample point too early and you read the bit while it is still arriving from the far node or still ringing; put it consistently and late, after the line has quieted, and every node reads the same value. A node whose bit rate is even slightly off, or whose sample point sits in the wrong place, will mis-sample and throw errors, which is exactly the trouble the next lesson untangles. For now, hold the rule: one bit rate for the whole bus, sampled near the end of each bit.

See it / Try it

The simulator below is the cold-resistance bench test made interactive. It draws a CAN trunk and lets you pull either end terminator out and watch two things at once: the multimeter reading across CANH-CANL, and the shape of the line as edges travel it. Start with both terminators in. The readout should sit at $60\ \Omega$, health “healthy,” and the trace should settle clean.

Now uncheck one terminator. The resistance jumps to $120\ \Omega$, the health flips to “one terminator only,” and the edges start to ring as the wave reflects off the open end. Uncheck the second and the bus goes effectively open, the reading runs very high, and the ringing gets ugly enough to corrupt bits. The lesson to carry off the screen: the resistance reading and the ringing are two views of the same fact. A bus that does not read near $60\ \Omega$ cold is a bus whose edges do not settle, and a bus whose edges do not settle drops frames. The cheap cold measurement predicts the expensive powered failure.

?On an unpowered CAN bus you measure 120 Ω across CANH and CANL. What does this most likely mean?

• A The bus is correctly terminated and healthy
• B Only one 120 Ω terminator is present; the other end is missing
• C Three terminators are installed and the bus is over-terminated
• D The transceivers are shorting CANH to CANL

?A receiver reads CANH = 3.5 V and CANL = 1.5 V. What is the differential voltage and which bit is this?

• A 0 V, recessive (logical 1)
• B 2 V, dominant (logical 0)
• C 5 V, dominant (logical 0)
• D 2.5 V, recessive (logical 1)

Lab: cold-check then watch the edge

Take the robot hand’s CAN harness with everything powered down. First, DMM across CANH-CANL at a connector and log the resistance: you are looking for about $60\ \Omega$. If you read $120\ \Omega$, walk the bus and find the end that lost its terminator; if you read near $40\ \Omega$, find the node that brought a terminator it should not have. Once the cold reading is healthy, power the bus, set a scope to differential (or a difference probe across CANH-CANL, per lesson 26) and trigger on a dominant bit. Confirm the recessive level sits near $0\ \text{V}$ differential and the dominant pulse reaches about $2\ \text{V}$, with edges that settle well before the sample point. Then, as a teaching exercise, deliberately pull one terminator and watch the same dominant edge ring. Log the cold resistance, the dominant differential voltage, and a photo of the clean versus ringing edge. That trio is your physical-layer signoff before you trust a single frame.

↘ Why 120 Ω, why twisted, and the asymmetry of the two edges

The $120\ \Omega$ is not arbitrary, and it is not really about limiting current. It is the characteristic impedance of the cable, the ratio of voltage to current that a fast wave sees as it propagates down a transmission line before it knows anything about what is at the far end. For a uniform line it depends only on the per-unit-length inductance and capacitance,

$$Z_0 = \sqrt{\frac{L}{C}},$$

set by the wire diameter, spacing, and the dielectric between them. CAN’s twisted pair is built to land near $120\ \Omega$. A wave meeting a resistor equal to $Z_0$ deposits all its energy there and reflects nothing; a wave meeting an open end (no terminator) reflects with the same sign and a wave meeting a short reflects inverted. The reflection coefficient $\Gamma = (Z_L - Z_0)/(Z_L + Z_0)$ is zero exactly when $Z_L = Z_0$, which is why the end resistor must match the line and why a single $120\ \Omega$ in the middle does not help, it absorbs energy that still has line to travel and leaves the ends unmatched.

The twisting matters for a different reason, the one from lesson 26. A twisted pair makes the two wires share, on average, the same path through space, so external interference couples onto both nearly equally as common-mode. The differential receiver subtracts the two wires and the shared interference cancels. Twisting also keeps the pair’s geometry, and therefore its impedance, uniform along the run, which keeps reflections small. Noise immunity on a CAN bus is bought with low-value termination and a balanced, twisted line together: the resistors kill reflections, the twist kills induced noise.

One subtle asymmetry to file away for the next lesson: the two edges of a CAN bit are not equally fast. The recessive-to-dominant edge is actively driven, transceivers shove the wires apart, so it is fast. The dominant-to-recessive edge is passive, the drivers let go and the termination resistors plus the line capacitance pull the wires back together, so its speed depends on the bus length and capacitance. That slower, passive falling edge is part of why CAN bit timing places the sample point late, at about $75$ to $87.5\%$, leaving time for the lazy edge and any residual ringing to settle before every node reads the bit.

Grounded in Wikipedia: “CAN bus”, “Twisted pair” (CC BY-SA). The authoritative course values (recessive $\approx 2.5\ \text{V}$ both wires, dominant CANH $\approx 3.5\ \text{V}$ / CANL $\approx 1.5\ \text{V}$, differential $\approx 2\ \text{V}$, $60\ \Omega$ cold) describe high-speed CAN per ISO 11898-2; the low-speed fault-tolerant variant (ISO 11898-3) uses larger swings and per-node termination, so its cold resistance does not land at $60\ \Omega$, a distinction the grounding text notes and we set aside here.

Key takeaways

• ▸CAN decides the bit from the differential voltage $V_\text{CANH} - V_\text{CANL}$, not from either wire against ground.
• ▸Recessive (logical 1): both wires near 2.5 V, differential ≈ 0 V, the idle/passive state. Dominant (logical 0): CANH ≈ 3.5 V, CANL ≈ 1.5 V, differential ≈ 2 V, actively driven, and dominant always wins.
• ▸Terminate with 120 Ω at each physical end of the trunk to absorb the wave and stop ringing; one terminator leaves half the energy reflecting.
• ▸Two 120 Ω ends in parallel read ≈ 60 Ω cold across CANH-CANL: the canonical health check. ≈ 120 Ω means one terminator is missing; ≈ 40 Ω means three.
• ▸Every node must share one bit rate and sample near 75-87.5% of the bit, after the line has settled, because CAN carries no separate clock.

Practice 1 warm-up

You power down a CAN bus and measure the resistance across CANH and CANL. The bus is built correctly with one terminator at each end. What value do you expect, and why that value?

↘ Show worked solution

About $60\ \Omega$. Each end carries a $120\ \Omega$ resistor bridging CANH to CANL, and with the bus unpowered those two resistors are simply in parallel across the same two wires:

$$R = \frac{120 \times 120}{120 + 120} = \frac{120}{2} = 60\ \Omega.$$

So a healthy, unpowered two-terminator bus reads about $60\ \Omega$. Reading $120\ \Omega$ instead would say only one terminator is present.

Practice 2 core

During a dominant bit a logic analyzer captures CANH = 3.4 V and CANL = 1.6 V. Compute the differential voltage and the common-mode voltage, and state which bit the receiver reads. The receiver’s recessive threshold is 0.5 V.

↘ Show worked solution

$V_\text{diff} = V_\text{CANH} - V_\text{CANL} = 3.4 - 1.6 = 1.8\ \text{V}$. $V_\text{cm} = (V_\text{CANH} + V_\text{CANL})/2 = (3.4 + 1.6)/2 = 2.5\ \text{V}$. The differential voltage of $1.8\ \text{V}$ is well above the $0.5\ \text{V}$ recessive threshold, so the receiver reads a dominant bit (logical 0). The $2.5\ \text{V}$ common-mode sits right at the bus center and is rejected by the differential receiver. (It is slightly under the nominal $2\ \text{V}$ swing, but comfortably dominant.)

Practice 3 stretch

A coworker adds a third node to a working two-terminator CAN bus and, because the breakout board they bought has a built-in $120\ \Omega$ terminator they did not notice, frames start to glitch. With the bus unpowered, what resistance would you now measure across CANH-CANL, what is the fault, and how do you fix it?

↘ Show worked solution

There are now three $120\ \Omega$ terminators in parallel across the same two wires:

$$R = \frac{120}{3} = 40\ \Omega.$$

So the cold reading drops from the healthy $60\ \Omega$ to about $40\ \Omega$. The bus is over-terminated. The parallel resistance is too low, so the transceivers have to sink more current to develop the dominant differential voltage, the dominant level sags toward the recessive threshold, and marginal bits glitch. The fix is to remove or disable the extra terminator (cut the jumper / remove the resistor on the new breakout board) so the bus is back to exactly two terminators at the two physical ends and reads $60\ \Omega$ again. Rule of thumb: only the two physical ends of the trunk get a terminator, never a node in the middle.