⬆️ I²C Open-Drain & Pull-Up Sizing

Every other bus you have met so far had a transmitter that could shove the line both ways. I²C cannot. Its devices can only pull down, so the journey back up is left entirely to a resistor charging the bus capacitance. That single design choice is what makes pull-up sizing the whole game: too big a resistor and the line rises too slowly, too small and you ask the chip to sink more current than it can. The right value lives in the narrow gap between those two failures, and the order to reason about it is fixed: rise time first, sink current second, scope last.

By the end, you can

1. Explain why an open-drain bus needs an external pull-up and what each device can and cannot drive
2. Calculate the bus rise time from R and C and compare it against the per-speed spec limit
3. Choose an upper bound on R from the rise-time budget and a lower bound from the 3 mA sink limit
4. Size pull-ups for a 400 kHz bus end to end: estimate C, pick R, verify both bounds, confirm on the scope

Intuition first

Picture the data line as a bucket and the logic threshold as a fill mark partway up its side. Every device on the bus has a drain plug at the bottom: open the plug and the bucket empties almost instantly to the floor (a clean, fast logic zero). No device has a tap. The only way water ever rises back to the fill mark is a thin pipe at the top, dribbling in from a reservoir. That pipe is the pull-up resistor, and the bucket’s width is the bus capacitance.

Now the tension is obvious. A wide pipe (small resistor) refills the bucket fast, so the line snaps high in time for the next clock edge. But a wide pipe also means that when a device opens its plug, it has to drain not just the bucket but the water still pouring in through the pipe, and a real plug can only swallow so much. A narrow pipe (large resistor) is gentle on the plug but refills the bucket so slowly that the fill mark arrives late, after the receiver has already looked away.

The art of pull-up sizing is choosing a pipe wide enough to refill in time but narrow enough that any single plug can still hold the line on the floor. Everything below is just putting numbers on “in time” and “on the floor.”

Open drain: pull low, never high

Look at how an I²C output is actually built. Each device hangs a single N-channel MOSFET on the shared wire, with its source at ground and its drain on the line. Drive the gate high and the transistor turns on, yanking the line down to nearly zero volts: a logic zero. Drive the gate low and the transistor turns off, going high-impedance, electrically disconnected from the wire. That is the entire output stage. There is no second transistor reaching up toward the supply. This is the open-drain configuration (its bipolar cousin, with a BJT instead of a FET, is called open-collector, and behaves identically for our purposes).

Because no device can push the line high, an external pull-up resistor to the supply rail does that job for the whole bus. When every device on the line is high-impedance, the resistor quietly pulls the wire up to the supply, and the bus reads a logic one. The instant any one device turns its FET on, that device wins: it sinks current straight to ground and the line goes low regardless of what anyone else wants. This is exactly why I²C can share two wires among many chips without short circuits. Two push-pull drivers fighting (one high, one low) would be a dead short and a puff of smoke. Two open-drain drivers can never fight, because neither can drive high. The worst they can do is both pull low, which is just a stronger zero.

That single picture explains three things at once. It is why the bus has a deterministic loser in arbitration (the device trying to send a one sees the line held low by someone sending a zero, and backs off). It is why a slow device can stretch the clock by simply holding SCL low until it is ready. And it is why the rising edge is the slow, fragile one: falling edges are a transistor slamming the line down, but rising edges are only a resistor trickling charge up.

Rise time: the bus is an RC charging up

When every device releases the line, the pull-up resistor $R$ has to charge the total bus capacitance $C_{bus}$ from zero up to the supply. That is exactly the RC charge you met back in the capacitor lesson: an exponential approach toward the rail with time constant $\tau = R \, C_{bus}$. The voltage climbs as

$$V(t) = V_{dd}\left(1 - e^{-t/(R\,C_{bus})}\right)$$

and the bus does not care about the whole curve. It cares about one thing: how long the edge takes to cross from a solid low to a solid high, the rise time $t_{rise}$, measured between the 30 percent and 70 percent points the I²C spec uses for this purpose. Working that band out of the exponential gives the rule you will use every time:

$$t_{rise} \approx 0.85 \, R \, C_{bus}$$

Read it as: the rise time is just under one RC time constant. Double the resistor, double the rise time. Double the capacitance (more devices, longer traces), double the rise time. The factor $0.85$ comes straight from the logarithms of those two threshold crossings, and it is close enough to one that you can sanity-check any design in your head: $t_{rise}$ is roughly $R$ times $C$.

The spec then sets a ceiling. The edge must finish well inside one bit period, so faster buses demand faster edges:

Bus speed	Maximum $t_{rise}$
100 kHz (standard)	$\approx 1\ \mu s$
400 kHz (fast)	$\approx 300\ \text{ns}$
1 MHz (fast-plus)	$\approx 120\ \text{ns}$

Your job is to keep the computed $t_{rise}$ comfortably under the row that matches your bus speed. Because $t_{rise}$ grows with $R$, that ceiling becomes an upper bound on the pull-up: any resistor bigger than

$$R_{max} \approx \frac{t_{rise,\text{spec}}}{0.85 \, C_{bus}}$$

makes the edge too slow. More devices and longer wires raise $C_{bus}$, which pushes $R_{max}$ down, so a crowded bus forces a smaller pull-up. That is the single most common cause of a bus that worked on the bench with one sensor and died when you added three more: the capacitance crept up and the old resistor stopped being fast enough.

Sink current: the floor under the resistor

So make the resistor small and the edges get fast. Why not use 100 Ω and be done? Because of the other end of the line. Remember that a logic zero is one device’s FET pulling the wire to ground against the pull-up, which is still trying to lift it. The smaller the resistor, the more current it forces back through that FET, and the FET can only sink so much while still holding the line genuinely low.

The spec pins this down with the low-level output voltage, $V_{OL}$. A compliant I²C device must be able to hold the line at or below $0.4\ \text{V}$ while sinking up to about $3\ \text{mA}$. At the worst case, the entire supply sits across the pull-up while the device clamps the bottom, so the current the FET must swallow is

$$I_{sink} \approx \frac{V_{dd}}{R}$$

Set that equal to the $3\ \text{mA}$ limit and you get a lower bound on the resistor:

$$R_{min} \approx \frac{V_{dd}}{3\ \text{mA}}$$

For a 3.3 V bus that is about $1.1\ \text{k}\Omega$; for 5 V, about $1.7\ \text{k}\Omega$. Go below $R_{min}$ and the device can no longer drag the line under $0.4\ \text{V}$, so your “zero” reads as a marginal half-volt that the next chip may or may not believe. You have not gained speed; you have manufactured an intermittent fault.

Now the whole problem has shape. The pull-up must live in a window:

$$\frac{V_{dd}}{3\ \text{mA}} \;\le\; R \;\le\; \frac{t_{rise,\text{spec}}}{0.85 \, C_{bus}}$$

The floor comes from sink current, the ceiling from rise time, and a healthy bus has a comfortable gap between them. When the gap closes, the message is not “try another resistor,” it is “you have too much capacitance for this speed.” For most hobby and robot-hand buses the classic $4.7\ \text{k}\Omega$ sits safely inside the window at 100 kHz, but as you will see in a moment, it can fall right off the ceiling at 400 kHz.

See it: drive the tug of war

The simulator below is the window made live. You set the pull-up $R$, the estimated bus capacitance $C_{bus}$, and the bus speed; it computes the rise time from $0.85\,R\,C_{bus}$, compares it to the spec limit for that speed, and reports the worst-case sink current $V_{dd}/R$ at the same time. Watch the two readouts move in opposite directions as you drag $R$: that opposition is the trade-off.

Start where it opens: $4.7\ \text{k}\Omega$, $100\ \text{pF}$, 400 kHz. The rise time lands near 400 ns against a 300 ns ceiling, so the verdict is FAIL, even though the sink current is a lazy 0.7 mA. The classic resistor is too slow here, not too greedy. Now drag $R$ down toward $2\ \text{k}\Omega$ and watch the rise time drop under the limit and flip to PASS while the sink current climbs toward 1.7 mA, still well under the 3 mA floor. You have just found a legal value by hand. Then push $C_{bus}$ up to 300 pF (imagine adding two more sensors and a cable) and watch the rise time balloon again: the same resistor that passed now fails, and you have to drop $R$ further still. That is the crowded-bus failure mode playing out in real time, and it is the single most useful intuition this lesson can give you.

?On an idle I²C bus with every device released, what is actually pulling the SDA line up to a logic one?

• A The controller's push-pull output driving the line high
• B Whichever device most recently transmitted, holding the line
• C The external pull-up resistor charging the bus capacitance toward Vdd
• D Nothing. The line floats and the receiver guesses

?You move a working 100 kHz bus up to 400 kHz and the rise time now exceeds the 300 ns spec. Which change fixes it while staying legal?

• A Increase the pull-up resistance to slow the edge gracefully
• B Decrease the pull-up resistance, then check it stays above Vdd / 3 mA
• C Add a second pull-up in series with the first
• D Lower the supply voltage so the line has less distance to climb

Lab: a five-minute pull-up sizing pass

At the bench, size pull-ups in the same order every time so you never get trapped. First, estimate $C_{bus}$: count roughly 10 pF per device pin plus the trace and any cable, and round up (it is always more than you think). Second, set the ceiling: take your bus speed’s $t_{rise}$ limit and compute $R_{max} = t_{rise}/(0.85\,C_{bus})$. Third, set the floor: $R_{min} = V_{dd}/3\ \text{mA}$, about $1.1\ \text{k}\Omega$ at 3.3 V. Pick a standard resistor near the middle of the $R_{min}$-to-$R_{max}$ window, leaning toward the smaller end if the bus is busy. Finally, confirm on the scope: probe SDA, look at a rising edge, and measure the real 30-to-70 percent time. If it is under the limit with margin and the low level sits under 0.4 V, you are done. If the edge is lazy, halve the resistor and re-measure. The scope is the judge; the math just gets you close.

↘ Where 0.85 comes from, and why fast-plus mode swaps the resistor for a current source

The factor $0.85$ is not magic; it falls out of the exponential charge. The I²C spec measures rise time between $0.3\,V_{dd}$ and $0.7\,V_{dd}$. Solving $V(t)=V_{dd}(1-e^{-t/\tau})$ for those two crossings:

$$t_{30} = -\tau \ln(1 - 0.3), \qquad t_{70} = -\tau \ln(1 - 0.7)$$$$t_{rise} = t_{70} - t_{30} = \tau\left[\ln(0.7) - \ln(0.3)\right] = \tau \ln\!\left(\tfrac{0.7}{0.3}\right) \approx 0.847\,\tau$$

so $t_{rise} \approx 0.85\,R\,C_{bus}$ exactly. (If you instead use the classic 10-to-90 percent band common elsewhere in electronics, the same algebra gives the familiar $t_{rise}\approx 2.2\,\tau$; I²C just samples a narrower, easier band, so its constant is smaller. Both describe the same RC edge.)

This also explains the spec’s escape hatch at high speed. As you push toward 1 MHz fast-plus and beyond, $R_{max}$ from the rise-time budget shrinks until it collides with $R_{min}$ from the sink limit, and no resistor satisfies both. The spec’s answer is to stop using a plain resistor. Fast-mode-plus drivers are specified to sink up to 20 mA (not 3 mA), which lowers $R_{min}$ and reopens the window; and high-speed mode allows a current-source pull-up that delivers constant charging current instead of a resistor’s ever-weakening trickle, flattening the late part of the edge that an RC curve drags out. Both are the same realization this lesson started with: the rising edge is the enemy, so spend transistors to fix it rather than over-constraining the resistor. A small note on the numbers: this lesson uses the practical $3\ \text{mA}$ sink figure and the $0.85$ rise-time constant as the working rules of thumb. Some grounding sources quote the wider 10-to-90 percent rise convention and mode-specific drive strengths (3 mA for standard and fast, 20 mA for fast-plus); those are consistent with the bounds here once you match the threshold band and the mode, and the authoritative numbers above are what to size with.

Grounded in Wikipedia: “I²C”, “Open collector”, “Rise time” (CC BY-SA).

Key takeaways

• ▸I²C is open-drain: every device can only pull the line LOW, and a single external pull-up provides the only path HIGH.
• ▸The rising edge is an RC charge: t_rise ≈ 0.85 · R · C_bus, and it must stay under ≈1 µs at 100 kHz, 300 ns at 400 kHz, 120 ns at 1 MHz.
• ▸Rise time puts an upper bound on R; smaller R means faster edges but more sink current.
• ▸Sink current puts a lower bound: R_min ≈ V_dd / 3 mA, because a device must hold the line under 0.4 V while sinking ≤ 3 mA.
• ▸More devices and longer traces raise C_bus, forcing a smaller R, and past 400 pF the window slams shut.

Practice 1 warm-up

A 100 kHz bus has a pull-up of $4.7\ \text{k}\Omega$ and an estimated bus capacitance of $120\ \text{pF}$. Estimate the rise time and say whether it passes the standard-mode limit.

↘ Show worked solution

Use $t_{rise} \approx 0.85\,R\,C_{bus}$:

$$t_{rise} \approx 0.85 \times 4700\ \Omega \times 120\times10^{-12}\ \text{F} \approx 0.85 \times 5.64\times10^{-7}\ \text{s} \approx 480\ \text{ns}$$

The standard-mode limit is about $1\ \mu s$, and $480\ \text{ns}$ is comfortably under it. The bus passes at 100 kHz. (Note that the same resistor and capacitance would fail at 400 kHz, where the ceiling is only 300 ns, which is why moving an existing bus to fast mode so often breaks it.)

Practice 2 core

Size the pull-ups for a 400 kHz bus running off 3.3 V with an estimated $C_{bus} = 200\ \text{pF}$. Find the rise-time upper bound on $R$, the sink-current lower bound, and pick a sensible standard resistor.

↘ Show worked solution

Upper bound (rise time). The 400 kHz ceiling is $t_{rise} = 300\ \text{ns}$:

$$R_{max} \approx \frac{t_{rise}}{0.85\,C_{bus}} = \frac{300\times10^{-9}}{0.85 \times 200\times10^{-12}} \approx \frac{3.0\times10^{-7}}{1.7\times10^{-10}} \approx 1.76\ \text{k}\Omega$$

Lower bound (sink current). With $V_{dd} = 3.3\ \text{V}$ and the 3 mA limit:

$$R_{min} \approx \frac{V_{dd}}{3\ \text{mA}} = \frac{3.3}{0.003} \approx 1.1\ \text{k}\Omega$$

Pick. The legal window is roughly $1.1\ \text{k}\Omega \le R \le 1.76\ \text{k}\Omega$. A standard $1.5\ \text{k}\Omega$ resistor sits neatly in the middle. Check it back: $t_{rise} \approx 0.85 \times 1500 \times 200\text{p} \approx 255\ \text{ns}$ (under 300 ns, pass) and $I_{sink} \approx 3.3/1500 \approx 2.2\ \text{mA}$ (under 3 mA, pass). Then confirm the real edge on the scope.

Practice 3 stretch

On a 3.3 V, 400 kHz bus you keep adding sensors and the capacitance has climbed to $C_{bus} = 600\ \text{pF}$. Show that no single resistor can satisfy both bounds, and say what you would actually do.

↘ Show worked solution

Rise-time ceiling at 300 ns:

$$R_{max} \approx \frac{300\times10^{-9}}{0.85 \times 600\times10^{-12}} \approx \frac{3.0\times10^{-7}}{5.1\times10^{-10}} \approx 588\ \Omega$$

Sink-current floor:

$$R_{min} \approx \frac{3.3}{0.003} \approx 1.1\ \text{k}\Omega$$

Now $R_{max} \approx 588\ \Omega$ is below $R_{min} \approx 1.1\ \text{k}\Omega$: the window has inverted, so there is no resistor that is both fast enough and gentle enough. The numbers are telling you the problem is not the resistor, it is the 600 pF (already well past the 400 pF spec wall). The real fixes: cut the capacitance (shorter traces, drop a sensor or two off this segment, lose the long cable), split the bus into segments behind an active bus buffer / repeater so each side sees less capacitance, or move to fast-mode-plus parts whose 20 mA drive lowers $R_{min}$ and reopens the window. Chasing a magic resistor here is wasted time.