🔌 Decoupling & the Power Distribution Network

Every active chip pulls current in bursts, not smoothly, and the wires feeding it have resistance and inductance that turn those bursts into voltage dips. Decoupling is the craft of placing small reservoirs of charge close enough to absorb the bursts before they become noise. The whole subject organizes itself around one idea: think of the power network as an impedance you are trying to keep low across every frequency the chip cares about, and place capacitors to fill in the gaps.

By the end, you can

1. Explain why a decoupling capacitor acts as a local battery for a chip's fast current transients
2. Define the power distribution network's target impedance and decide whether a rail meets it
3. Relate a capacitor's self-resonant frequency to its ESL and explain why staggered values cover a wider band
4. Calculate the voltage dip a placement adds from mounting inductance, and justify minimizing loop area
5. Size decoupling for the 170 mA Wi-Fi transmit burst

Intuition first

Picture the power supply as a water tower across town and the chip as a house that occasionally needs a huge gulp of water all at once. The pipe from the tower has length and friction, so when the house opens a fire hose the pressure at the tap sags for a moment before the tower’s pressure works its way down the pipe. The fix any plumber would reach for is a small tank in the basement, full and ready, that supplies the gulp instantly and refills slowly through the long pipe afterward.

A decoupling capacitor is that basement tank. Charge is the water, voltage is the pressure, and the long pipe is the resistance and inductance of the copper between the regulator and the chip. When the chip demands a fast burst, the nearby capacitor empties a little to hold the voltage steady, then the slower regulator refills it. The closer the tank sits to the tap, the less pipe stands between them, and the better it works.

Here is the catch that makes decoupling an actual craft rather than a single rule: no single tank is good at every timescale. A big tank holds a lot of water but has a wide, slow inlet, so it cannot respond to a flick-fast demand. A tiny tank responds instantly but runs dry. Real power networks use both, plus the geometry of the plumbing matters as much as the tank sizes. That is the whole lesson in one sentence: bulk for slow demand, small ceramics right at the pin for fast demand, placed to keep the loop tiny.

The power distribution network and its target impedance

The chain from regulator to chip pin (the regulator, the copper planes, the vias, the capacitors, the pad) is called the power distribution network, or PDN. Stop thinking of it as a wire and start thinking of it as one big frequency-dependent impedance the chip sees looking back toward its supply. Call that impedance $Z(f)$.

Why impedance? Because the chip’s current demand is not one number, it is a spectrum. Slow average draw, a kilohertz wiggle as a control loop runs, a megahertz burst when the radio keys up, all at once. Each of those frequency components hits the PDN impedance and produces a voltage ripple by Ohm’s law in its AC form:

$$\Delta V(f) = I(f) \cdot Z(f)$$

If the chip can tolerate a ripple of $\Delta V_{\text{max}}$ and might pull a transient of $\Delta I$, then the impedance you are allowed at every frequency the chip cares about is bounded:

$$Z_{\text{target}} = \frac{\Delta V_{\text{max}}}{\Delta I}$$

This is the single most useful number in the whole subject. Suppose a 3.3 V rail must stay within 3 percent, so $\Delta V_{\text{max}} = 0.10\ \text{V}$, and the worst-case transient is the $\Delta I = 0.17\ \text{A}$ Wi-Fi burst. Then

$$Z_{\text{target}} = \frac{0.10\ \text{V}}{0.17\ \text{A}} \approx 0.6\ \Omega .$$

The design job becomes concrete: keep $|Z(f)|$ of the PDN below about 0.6 Ω from DC up through the frequencies in that current burst. Below the target, the rail holds. Anywhere $|Z|$ pokes above the target, that frequency of current draw will make a dip big enough to glitch the chip.

Why one capacitor is never enough: self-resonance

An ideal capacitor’s impedance falls forever as frequency rises: $Z_C = 1/(2\pi f C)$. Real capacitors are not ideal. Every real part is a capacitance in series with two parasites: a small resistance (the equivalent series resistance, ESR) and a small inductance from its leads, body, and the copper that mounts it (the equivalent series inductance, ESL). So a real capacitor is an R-L-C series chain, and its impedance magnitude is

$$|Z| = \sqrt{ \text{ESR}^2 + \left( 2\pi f\,\text{ESL} - \frac{1}{2\pi f C} \right)^2 } .$$

At low frequency the capacitive term $1/(2\pi f C)$ dominates and $|Z|$ falls as you would expect. At high frequency the inductive term $2\pi f\,\text{ESL}$ dominates and $|Z|$ rises again. In between, the two cancel and the impedance bottoms out at just the ESR. That crossover is the self-resonant frequency:

$$f_{\text{SRF}} = \frac{1}{2\pi \sqrt{\text{ESL} \cdot C}} .$$

Below $f_{\text{SRF}}$ the part is a capacitor and helps you. Above $f_{\text{SRF}}$ the part is an inductor and stops helping. A big bulk capacitor has a low $f_{\text{SRF}}$ (large $C$), so it covers the low end and goes inductive early. A small ceramic has a high $f_{\text{SRF}}$, so it stays capacitive much further up. Neither covers the whole band alone.

The answer is to stagger values in parallel: a 100 µF bulk part for the slow demand, plus one or more small ceramics (say 100 nF and 1 nF) whose self-resonances march up the frequency axis. Each cap owns the band around its own resonance, and the parallel set keeps $|Z|$ low across a decade or more that no single part could cover. The bulk cap is the basement tank; the ceramics are the tiny fast tanks at the tap.

Placement: the loop you forgot to count

Here is the part that trips up every first board. You can pick perfect capacitor values and still get a useless PDN, because the ESL is not just inside the part. It is mostly in how you mount it. Every loop of current, out the via to the pad, through the cap, back the return via to the plane, encloses an area, and any loop of area has inductance. A capacitor placed a centimeter from the pin, with long traces and far-apart vias, adds far more mounting inductance than the part’s own internal ESL.

That mounting inductance is in series with the cap, so it pushes the self-resonant frequency down and raises the high-frequency floor. A cap placed far from the pin loses its entire high-frequency benefit to mounting inductance even though its capacitance is unchanged. The number on the part is a promise the layout can break.

The voltage you pay for that inductance is brutal at high $di/dt$. An inductance $L$ develops a voltage when current changes:

$$V_L = L \frac{di}{dt} .$$

Suppose the Wi-Fi burst rises by 0.17 A in 10 ns (a $di/dt$ of $1.7 \times 10^{7}$ A/s), and a sloppy placement adds 2 nH of loop inductance. The spike across that loop is

$$V_L = 2\times 10^{-9}\ \text{H} \cdot 1.7\times 10^{7}\ \tfrac{\text{A}}{\text{s}} \approx 0.034\ \text{V} = 34\ \text{mV}$$

from the mounting alone, on top of everything else. Halve the loop area and you roughly halve that spike for free. So the rules of placement all reduce to one geometric goal: minimize loop area. Put the ceramic against the pin, short fat traces to the pad, the return via as close to the supply via as the rules allow, and let the ground plane carry the return directly underneath. The bulk cap can sit a little farther back because it owns only the low frequencies, where a few extra millimeters of inductance barely matter.

See it / try it

The simulator below plots $|Z(f)|$ of a small PDN as you build it. The dashed line is your target impedance; red bands mark frequencies where the network is over budget. Start with just the bulk electrolytic, then stack ceramics and watch the high end fill in. Then flip the placement from near to far and watch the same parts lose their grip on the top decade.

Three things to notice. First, the bulk cap alone holds the low frequencies but lets $|Z|$ climb above target at the top, exactly where the fast Wi-Fi burst lives. Second, adding ceramics drags the high-frequency end back under the line, and each one carves out the band near its own self-resonance, with little anti-resonant bumps appearing between them. Third, moving the caps far from the pin raises the whole high-frequency floor: same capacitance, worse PDN, because mounting inductance ate the benefit. Lowering the target line shows how a twitchier chip (smaller tolerable dip) demands either more parallel caps or tighter placement, or both.

?A 3.3 V rail must stay within 0.10 V and the worst transient the chip pulls is 0.17 A. What target impedance must the PDN beat across the burst's frequency band?

• A About 0.6 Ω
• B About 1.9 Ω
• C About 17 Ω
• D It cannot be computed without the capacitor value

?You move a 100 nF ceramic from right at the IC pin to a centimeter away with long traces. Its capacitance is unchanged. What happens to its decoupling performance?

• A Nothing, since the capacitance is the same
• B It improves, because longer traces add helpful resistance
• C Its high-frequency benefit drops, because added mounting inductance lowers its self-resonant frequency
• D It only matters for the bulk capacitor, not for ceramics

Lab: probe the dip at the pin

To see decoupling do its job, AC-couple a fast scope probe with the shortest possible ground tip and put it right on the chip’s supply pin, not at the regulator. Trigger on the Wi-Fi transmit event (or on a GPIO you toggle just before the radio keys up). On a board with only a bulk cap you will see a sharp negative spike, the brownout dip, tens of millivolts deep and a few microseconds wide. Solder a 100 nF ceramic across the pin pads and the spike shrinks; the closer you mount it, the more it shrinks. Then deliberately add a length of wire between the cap and the pin and watch the spike grow back. That single bench experiment teaches the whole lesson: the part value sets the band, the placement sets whether you actually get it.

↘ The full lumped model, anti-resonance, and why the PCB itself is a capacitor

A decoupling capacitor’s job is to give transient currents a low-impedance bypass path to ground so they do not have to travel through the long, inductive common path back to the supply. Without it, a current change $di/dt$ in one chip drops a voltage across the shared supply inductance and that dip is coupled into every other chip on the same rail, the ground bounce and supply spikes that show up as logic glitches. The capacitor decouples the chips from each other by absorbing the burst locally.

Each real capacitor is the series R-L-C we used above. Two such caps in parallel do not simply give a lower impedance everywhere. Near the frequency where the smaller cap is still capacitive (negative reactance) and the larger cap has already gone inductive (positive reactance), the two reactances cancel as a parallel resonance and the combined impedance peaks. This is the anti-resonance bump, and a PDN built from many staggered caps has one between each pair. ESR is what tames them: the loss in the loop limits how high the peak can climb. This is the counterintuitive result that a slightly lossy capacitor can make a better PDN than a perfect one, because the loss damps the anti-resonant spikes. The ESR of a ceramic is roughly 0.01-0.1 Ω; aluminum electrolytics run up to several ohms and that ESR itself rises as the part ages and the electrolyte dries, which is one way a board that worked for years slowly starts glitching.

The asymptotic geometry is worth memorizing. On a log-log impedance plot a single cap is a downward slope (capacitive, $-20$ dB/decade), a notch at $f_{\text{SRF}}$ whose depth is the ESR, and an upward slope (inductive, $+20$ dB/decade). The PDN designer’s whole job is to stack enough of these notches, with enough damping, that the jagged envelope stays under the flat target line from DC to the highest frequency in the load current.

There is a final reservoir most people forget: the board itself. Power and ground planes separated by a thin dielectric form a parallel-plate capacitor spread across the whole board. It is small in absolute terms but it is everywhere, with essentially zero mounting inductance, so it is the fastest reservoir of all and handles the very highest frequencies that even a tiny ceramic, with its own ESL, cannot reach. Designing the stackup so the power and ground planes are close together is the cheapest decoupling capacitor you will ever place.

Grounded in Wikipedia: “Decoupling capacitor”, “Equivalent series resistance” (CC BY-SA). The authoritative facts for this course fix the target-impedance framing and the 170 mA Wi-Fi burst as the transient to design against; where Wikipedia’s general “noise shunt” description is looser, the target-impedance view above is the one to keep.

Key takeaways

• ▸A decoupling capacitor is a local battery: it supplies a chip's fast current burst on the spot, then recharges slowly from the regulator.
• ▸Design to a PDN target impedance $Z_{\text{target}} = \Delta V_{\text{max}} / \Delta I$, and keep $|Z(f)|$ below it across the load's frequency band.
• ▸Real caps are R-L-C: each has a self-resonant frequency below which it is capacitive and above which ESL makes it inductive, so you stagger values to cover a wide band.
• ▸Placement is half the part: mounting inductance from a distant cap kills its high-frequency benefit, so minimize loop area and put ceramics right at the pin.
• ▸A little ESR is useful: it sets the impedance floor at resonance and damps the anti-resonance bumps between staggered caps.
• ▸Size the network against the worst transient, here the 170 mA Wi-Fi TX burst; bulk owns the slow demand, ceramics own the fast.

Practice 1 warm-up

A 1.8 V core rail can tolerate a 5 percent dip and the chip’s worst transient is 0.40 A. What target impedance must the PDN beat?

↘ Show worked solution

Five percent of 1.8 V is the allowed dip:

$$\Delta V_{\text{max}} = 0.05 \times 1.8\ \text{V} = 0.09\ \text{V}.$$

Target impedance is the allowed dip divided by the transient current:

$$Z_{\text{target}} = \frac{0.09\ \text{V}}{0.40\ \text{A}} = 0.225\ \Omega .$$

So the PDN must keep $|Z(f)|$ below about 0.23 Ω across the frequencies in that 0.40 A burst. A tighter rail (smaller percent) or a bigger transient would push this lower and demand more parallel caps or tighter placement.

Practice 2 core

A 100 nF ceramic has an equivalent series inductance (ESL) of 1.2 nH including its mounting. Estimate its self-resonant frequency. Above that frequency, is it still doing its job?

↘ Show worked solution

Use the self-resonance formula:

$$f_{\text{SRF}} = \frac{1}{2\pi\sqrt{\text{ESL}\cdot C}} = \frac{1}{2\pi\sqrt{(1.2\times10^{-9})(100\times10^{-9})}}.$$

The product under the root is $1.2\times10^{-16}$, whose square root is $1.095\times10^{-8}$. Then

$$f_{\text{SRF}} = \frac{1}{2\pi (1.095\times10^{-8})} \approx 1.45\times 10^{7}\ \text{Hz} \approx 14.5\ \text{MHz}.$$

Above roughly 14.5 MHz the inductive term $2\pi f\,\text{ESL}$ dominates and the part’s impedance rises with frequency, so it is acting like an inductor and no longer decoupling well. To cover frequencies above this you add a smaller ceramic with a higher self-resonance.

Practice 3 stretch

The 170 mA Wi-Fi burst turns on with a current slew of $di/dt = 2 \times 10^{7}$ A/s. Your first layout mounts the decoupling ceramic with 2.5 nH of loop inductance; a revised layout gets the loop down to 0.8 nH. Compute the inductive voltage spike for each, and say how much of the rail’s 0.10 V budget each one eats.

↘ Show worked solution

The inductive spike is $V_L = L\,(di/dt)$.

First layout:

$$V_L = 2.5\times10^{-9}\ \text{H} \times 2\times10^{7}\ \tfrac{\text{A}}{\text{s}} = 0.050\ \text{V} = 50\ \text{mV}.$$

That alone eats half of the 0.10 V budget, leaving little room for the resistive and bulk-cap contributions, this layout is marginal.

Revised layout:

$$V_L = 0.8\times10^{-9}\ \text{H} \times 2\times10^{7}\ \tfrac{\text{A}}{\text{s}} = 0.016\ \text{V} = 16\ \text{mV}.$$

Now the mounting spike is only 16 mV, about a sixth of the budget. Same capacitor, same value: shrinking the loop from 2.5 nH to 0.8 nH cut the spike by a factor of roughly three, purely by geometry. This is why “minimize loop area, place ceramics at the pin” is the rule that matters most.