Module 4: Single-Ended Buses: SPI & I²C
SPI modes and CS framing, I²C pull-up sizing, stuck-bus recovery, decode tooling.
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1conceptAn SPI peripheral datasheet specifies CPOL=1, CPHA=1. What must the controller be set to, and what defines those four SPI modes?
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Mode 0 is CPOL=0/CPHA=0; it does not match CPOL=1/CPHA=1, and clock speed does not define the mode.
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Correct. The four SPI modes (0–3) are exactly the CPOL/CPHA combinations; CPOL=1, CPHA=1 is Mode 3, and the controller must match the peripheral or every byte samples on the wrong edge.
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Mode 1 is CPOL=0/CPHA=1; CPOL/CPHA are precisely what select the mode, so they are not independent of it.
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A mismatched mode samples MOSI/MISO on the wrong clock edge and returns garbage even with CS correctly asserted.
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2conceptThree SPI peripherals share MOSI, MISO, and SCLK. What keeps their MISO outputs from colliding on the shared line?
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Correct. CS frames the transaction: a deselected SPI peripheral tri-states (high-Z) its MISO so only the one selected device drives the shared line.
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SPI has no in-band addressing; selection is by the dedicated CS line, not an address poll.
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SPI MISO is a push-pull output gated by CS, not an open-drain wired-OR like I²C.
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SPI does not time-slice the bus; the CS lines arbitrate which single peripheral may drive MISO.
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3calcAn I²C bus must meet a 300 ns rise-time limit and the bus capacitance is Cb = 200 pF. Using t_rise ≈ 0.85·R·Cb, what is the maximum pull-up resistance?
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530 Ω is far below the maximum; it gives a much faster edge but wastes sink current, so it is not the limit the constraint sets.
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Correct. R_max = t_rise / (0.85·Cb) = 300 ns / (0.85 × 200 pF) ≈ 1.76 kΩ, the largest pull-up that still meets the 300 ns rise time.
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3.5 kΩ would give t_rise ≈ 0.85 × 3.5 kΩ × 200 pF ≈ 595 ns, which violates the 300 ns limit.
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10 kΩ gives t_rise ≈ 1.7 µs, far beyond the 300 ns limit: the edge is far too slow.
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4conceptYou add several more I²C devices to a board and the bus stops working at the old pull-up value. Why, and what is the trade-off in shrinking the pull-up?
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Adding devices adds pin and trace capacitance, raising Cb, not lowering it.
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Correct. Each device adds capacitance, so Cb rises and the RC rise time grows; dropping R restores a fast edge but raises the current the driver must sink at VOL, bounded by the device's ~3 mA low-level sink limit.
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I²C has no CPOL/CPHA modes; that is SPI, and capacitance is the real cause here.
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There is no automatic compensation; the designer must size the pull-up against Cb and the VOL sink limit.
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5scenarioAn I²C peripheral glitched mid-byte and now holds SDA low, so the controller cannot generate a START. What is the standard recovery?
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A full power-cycle is a blunt last resort; the bus-clear procedure recovers without resetting everything else.
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Correct. Clocking SCL up to nine pulses lets the stuck peripheral finish shifting out its byte and release SDA, after which a STOP condition re-synchronizes the bus.
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Holding SDA low is the fault condition itself, not the fix; you must clock SCL to free the line.
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Clock frequency does not unstick a peripheral mid-byte; the device needs clock edges to advance, capped at nine, then a STOP.
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